1. Field of the Invention
The invention generally related to a method to manufacture semiconductors devices. More particularly, the invention related to a method to form semiconductor devices with reduced process steps.
2. Description of the Prior Art
As the functions of a semiconductor chip become more and more complicated, it usually comprises a variety of devices with different electrical characteristics.
The threshold voltage (Vt) represents the switching characteristic of a transistor, and it is crucial for the magnitude of drive current and off-state leakage current. Generally, devices may be classified according to their threshold voltage. For example, devices of the same type, such as MOS transistors having the same geometry but different threshold voltages, may be classified into low threshold voltage devices (LVT), regular threshold voltage devices (RVT) and high threshold voltage devices (HVT). It is a sophisticated task during semiconductor manufacturing to adjust the threshold voltage of a device to its target value to obtain expected electrical behavior and better performance.
The threshold voltage of a transistor depends on various properties, such as geometry size of the transistor, or material used to fabricate the transistor. The threshold voltage may also be adjusted by performing implantation, such as forming a Vt adjusting implant layer in the well region, or forming a pocket (halo) implant area in the channel region. Implantation to form the pocket implant area is usually performed at the stage after formation of the gate structure, and is incident from a direction with a particular tilt angle, which is defined as the subtended angle between the incident ion beam and the nominal axis of the wafer. The tilt angled implantation allows dopant in the ion beam to be implanted into the desired pocket implant area which is adjacent to the gate edge and overlapped by the gate structure. In a cross-sectional view taken along the channel direction of a transistor, two pocket implant areas are usually formed symmetrically at the two ends of the channel. Furthermore, to ensure that the tilted pocket implant would produce the same transistor regardless of their locations and orientations on the wafer, a wafer rotation is usually simultaneously carried out during the implant process.
Because the pocket implant is tilted at an angle, a nearby structure or sidewall of a resist layer may shadow part of the exposed area, preventing the dopant from implanting into the shadowed area. This phenomenon is referred to as “pocket shadowing” or “pocket blocking”, and usually results in undesirable deviations of the electrical characteristics of the transistor, such as a lower threshold voltage and a raised drive current which are not originally designed for the transistor. Therefore, such shadowing has traditionally been avoided to mitigate these undesirable deviations of the transistors by setting a proper tilt angle of the implant, or setting a minimum distance from the edge of resist layer to where is intended to be implanted.
In advanced semiconductor manufacturing, pocket implant area has been more frequently adopted for adjusting the threshold voltages of devices, for it may allow the scaling of the channel length to boost the drive current without the side effect of an increasing off-state leakage.
Generally, for devices with different threshold voltages, pocket implant areas of each of these devices are individually formed in different steps comprising different photo masks to define which areas are to be implanted, and different ion species or dosages specific for each of the devices.
For example, please refer to FIG. 1, which illustrates the conventional method to form pocket implant areas of, for example, two different devices 10 and 20. As shown in FIG. 1(a), a substrate 1 comprising at least a first device 10 and at least a second device 20 disposed in different areas is provided. There may be an isolation structure 2 between the active area 12 of the first device 10 and the active area 22 of the second device 20. In this case, the first device 10 and the second device 20 may have the same channel orientation, but in other cases, their channel orientations may be perpendicular to each other. As shown in FIG. 2(b), after forming their gate structures 11 and 21, a photolithography process and a following angled ion implantation process 13 are performed to implant the first device 10 which is exposed from an opening 31 of the mask layer 30. The second device 20 is covered by the mask layer 30, and would not be implanted by the angled ion implantation 13.
Subsequently, as shown in FIG. 1(c), after removing the mask layer 30, another photolithography process and another angled ion implantation process 23 is carried out, to implant the second device 20 which is exposed from a second opening 33 of the mask layer 32. This time, the first device 10 is covered by the mask layer 32, and would not be implanted by the angled ion implantation 23. After the ion implantation process 23, the mask layer 32 is removed too.
The angled ion implantation 13 and 23 may comprise different ion species and doping dosages, which are individually selected in accordance with the first device 10 and the second device 20. As a result, as shown in FIG. 1(d), by the two photography-implantation routes as previously described, pocket implant areas 10a and 10b of the first device 10 and pocket implant areas 20a and 20b of the second device 20 are formed respectively. As more and more devices are integrated into the same chip, conventional process aforesaid to form each device's pocket implant areas respectively may become time consuming. The tedious process not only reduces the productivity, but also has a higher risk to have defects, such as photo resistant residue, left on the wafer, resulting in yield loss. Therefore, there is still a need in the field to provide a method to form different devices with better time and cost efficiency.